1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and more particularly, the present invention relates to delay locked loop (DLL) circuits and to methods of generating clock signals using DLL circuits.
A claim of priority is made to Korean Patent Application No. 10-2006-0072291, filed on Jul. 31, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional delay locked loop (DLL) circuit 100 which functions to synchronize the phase of an input clock signal with the phase of a delayed output clock signal. As shown, the DLL circuit 100 includes a voltage controlled delay line (VCDL) 110, a phase detector 120, and a control voltage generator 130.
The VCDL 110 includes a plurality (e.g., four in FIG. 1) of delay elements which are connected in series, and a delay time of the VCDL 110 is controlled by a control voltage Vctrl output by the control voltage generator 130. The VCDL 110 delays an externally supplied reference clock signal ref_clk and generates a resultant output clock signal clk_out.
The phase detector 120 compares the phase of the reference clock signal ref_clk with the phase of the output clock signal clk_out and outputs an “up” signal and a “dn” signal in accordance with a comparison result. The control voltage generator 130 is responsive to the “up” and “dn” signals to increase and decrease the control voltage Vctrl, thereby controlling the delay time of VCDL 110. In this manner, output clock signal clk_out is made to synchronize with the reference clock signal ref_clk.
FIGS. 2A through 2C are timing diagrams for further explaining an operation of the DLL circuit 100 of FIG. 1. In the examples shown, the output clock signal clk_out is delayed by one clock cycle relative to the reference clock signal ref_clk. Referring to FIG. 2A, the phase detector 120 outputs the “up” signal when a leading edge of the clock signal ref_clk is advanced relative to a leading edge of the reference clock signal ref_clk, and the control voltage generator 130 is responsive thereto to decrease the delay of the VCDL 110. On the other hand, referring to FIG. 2B, the phase detector 120 outputs the “down” signal when the leading edge of the clock signal ref_clk lags behind the leading edge of the reference clock signal ref_clk, and the control voltage generator 130 is responsive thereto to increase the delay of the VCDL 110. Finally, as shown in FIG. 2C, neither the “up” signal nor the “down” signal is output by the phase detector 120 when the output clock signal clk_out is in phase with the reference clock signal ref_clk.
FIG. 3 is a circuit diagram of the control voltage generator 130 shown in FIG. 1. Referring to FIG. 3, the control voltage generator 130 includes a charge pump 131 and a loop filter 132. The charge pump 131 performs charge pumping in response to the “up” signal and the “dn” signal. In operation, when the “up” signal is at a high level, a switch 31 is turned on and current is supplied from a current source 33 to charge one or more capacitive elements of the loop filter 132, thereby increasing the control voltage Vctrl. On the other hand, when the “dn” signal is at a high level, a switch 32 is turned on and current is discharged from the one or more capacitive elements of the loop filter 132 via a current source 34, thereby decreasing the control voltage Vctrl. The switches 31 and 32 may, for example, be implemented by a PMOS transistor and an NMOS transistor, respectively. The current sources 33 and 34 may, for example, also be implemented by a PMOS transistor and an NMOS transistor, respectively.
The loop filter 132 functions a low-pass filter which removes alternating current (AC) components from the control voltage Vctrl.
When the phase of the reference clock signal ref_clk is the same as the phase of the output clock signal clk_out, the phase detector 120 does not output a pulse stream (see FIG. 2C) and the delay of the VCDL 110 is held constant. This state is referred to as a locking state in which the DLL circuit 100 desirably outputs a stable clock signal. Accordingly, it is important to enter the locking state quickly. In practicality, however, it takes multiple clock cycles for the conventional DLL circuit 100 to achieve a locking state. Further, as explained next, the conventional DLL circuit 100 has a limited locking range locking range.
FIGS. 4A and 4B are timing diagrams for explaining the locking range limits of the conventional DLL circuit 100. In the figures, the DLL circuit 100 is designed to delay the reference clocks signal ref_clk by a time period Tref equal to one clock cycle.
FIG. 4A illustrates the case where the leading edge of the output clock signal clk_out lags behind the leading edge of the reference clock signal ref_clk by an amount exceeding 0.5 Tref (one-half clock cycle). In this state, the phase detector 120 erroneously outputs the “up” signal, which causes the output clock signal to further lag behind the reference clock signal ref_clk. Eventually, a state is reached where the VCDL circuit is set to a minimum delay time Tdmin, the “up” signal is repeatedly output from the phase detector 120 at each clock cycle, and a locking state thus cannot be realized.
FIG. 4B illustrates the case where the leading edge of the output clock signal clk_out is advanced beyond the leading edge of the reference clock signal ref_clk by an amount exceeding 0.5 Tref (one-half clock cycle). In this state, the phase detector 120 erroneously outputs the “dn” signal, which causes the output clock signal to further advance ahead of the reference clock signal ref_clk. Eventually, a state is reached where the VCDL circuit is set to a maximum delay time Tdmax, and the “dn” signal is repeatedly output from the phase detector 120 at each clock cycle. Thus, a locking state cannot be achieved.
In addition to exhibiting a limited locking range, the conventional DLL circuit 100 can suffer the drawback of unstable harmonic locking, for example, in which the output clock signal clk_out is locked two cycles out of phase (rather than one cycle) relative to the reference clock signal ref_clk.